A simulation analysis of quarter-micron CMOS LSI input circuit behavior under CDM-ESD for protection device improvement

Author

Narita, Kaoru ; Horiguchi, Yoko ; Hayano, Kiminori ; Suzuki, Kouichi

Author_Institution

Device Analysis Technol. Labs., NEC Corp., Kawasaki, Japan

fYear

1999

fDate

28-30 Sept. 1999

Firstpage

116

Lastpage

123

Abstract

The behavior of a quarter-micron CMOS LSI input circuit during charged device model (CDM) ESD has been investigated using a device simulator. The result clarifies the relationship between the protection device structure and the voltage difference that appears in the inner circuit and causes gate oxide breakdown. The result indicates that the most efficient protection device structure is an optimized lateral silicon-controlled rectifier (SCR). An improved structure that effectively prevents voltage increases in the internal circuits during CDM-ESD has been proposed for future CMOS LSI protection devices.

Keywords

CMOS integrated circuits; circuit simulation; dielectric thin films; electric breakdown; electrostatic discharge; integrated circuit modelling; integrated circuit reliability; large scale integration; protection; semiconductor diodes; solid-state rectifiers; 0.25 micron; CDM-ESD; CMOS LSI input circuit; CMOS LSI protection devices; SiO/sub 2/-Si; charged device model ESD; device simulator; gate oxide breakdown; inner circuit; internal circuits; optimized lateral silicon-controlled rectifier; protection device improvement; protection device structure; simulation analysis; voltage difference; Analytical models; Breakdown voltage; Circuit simulation; Electrostatic discharge; Large scale integration; Medical simulation; Parasitic capacitance; Protection; Substrates; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999

Conference_Location

Orlando, FL, USA

Print_ISBN

1-58637-007-X

Type

conf

DOI

10.1109/EOSESD.1999.818997

Filename

818997