Execution Objects for Dynamically Reconfigurable FPGA Systems

This paper explores the use of pre-routed cores as execution objects in an object-oriented programming model and execution environment for dynamic computing on FPGA. In order to maintain FPGA computing performance it is crucial to thoroughly analyze the issues at the lowest level of device detail in order to ensure that computing circuit encapsulation is as efficient as possible. The first methodology that allows a core to scale its interface bandwidth to the maximum available in a routing channel was presented. Cores can be constructed independently from the rest of the system using a framework that is independent of the method used to place and route primitive components within the core. The authors used an architecture model and CAD tools that mirror those used in industry. Abutting cores are instantly connected by co-location of interface wires. Eliminating run-time routing drastically reduces the time taken to construct a system using a set of cores. It was illustrated how, although pre-routing has an adverse impact on core performance by up to 14%, it can improve functional density by up to six times for rapid reconfiguration