A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies

Author

Voldman, S. ; Anderson, W. ; Ashton, R. ; Chaine, M. ; Duvvury, C. ; Maloney, T. ; Worley, E.

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

fYear

1999

fDate

28-30 Sept. 1999

Firstpage

212

Lastpage

224

Abstract

This paper proposes an ESD technology strategy for characterization, evaluation and benchmarking the ESD "robustness" of CMOS semiconductor technologies. The ESD methodology uses a set of CMOS "building block" ESD test structures, matrices of critical ESD layout variables, electrical characterization parameters, and testing and extraction procedures, and ESD metrics. This work is the first step in the development of a common ESD language.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit layout; integrated circuit reliability; integrated circuit technology; integrated circuit testing; matrix algebra; CMOS building block ESD test structures; CMOS semiconductor technologies; ESD methodology; ESD metrics; ESD robustness; ESD robustness characterisation; ESD robustness evaluation; ESD technology strategy; benchmarking; common ESD language development; critical ESD layout variables matrices; electrical characterization parameters; extraction procedures; testing procedures; Benchmark testing; CMOS technology; Circuit testing; Data mining; Electrostatic discharge; Foundries; Manufacturing; Microelectronics; Rivers; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999

Conference_Location

Orlando, FL, USA

Print_ISBN

1-58637-007-X

Type

conf

DOI

10.1109/EOSESD.1999.819064

Filename

819064