The Darpa Multiple Precision Arithmetic Benchmark on a Reconfigurable Computer

Benchmark one of the DARPA HPCS discrete mathematics suite for high productivity computing involves multiple precision arithmetic. The benchmark computes the product of two given N times N matrices whose entries are multiple precision integers, with the product being taken modulo another multiple precision integer M. The authors describe algorithms and methodologies for three implementations of this benchmark on SRC computers´ SRC-6 reconfigurable platform and present performance results. The use of pipeline parallelism from inner loops, parallel code sections, and the two FPGA chips on the SRC hardware can speed up performance by as much as 20times compared to a software only implementation