Title :
Dynamic Memory Sub-System for Reconfigurable Platforms
Author :
Ang, Su-Shin ; Constantinides, George
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll., London
Abstract :
The primary objective of the study is to automate the generation of a flexible memory sub-system to handle dynamic memory accesses. A secondary objective of the study is to evaluate and develop transformations for high-level design descriptions, due to the larger impact that these transformations have at high level of abstractions (Wilton, et al, 2005) over lower levels, as well as the need to maintain design time
Keywords :
automatic test pattern generation; cache storage; high level synthesis; logic design; reconfigurable architectures; automatic generation; dynamic memory access; dynamic memory sub-system; flexible memory sub-system; high-level design description transformation; reconfigurable platforms; Bandwidth; Clocks; Degradation; Educational institutions; Field programmable gate arrays; Logic; Motion estimation; Read-write memory; Scanning probe microscopy; Switches;
Conference_Titel :
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Conference_Location :
Madrid
Print_ISBN :
1-4244-0312-X
DOI :
10.1109/FPL.2006.311349
