Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware

In this paper an area efficient multiplier-less hardware architecture is proposed for the implementation of an integrate- and-fire SNN model. The proposed architecture is intended for large scale implementation on a single FPGA. A modular design is proposed in order to make it flexible. Synaptic multiplication is performed with a simple AND gate, and pulses from different synapses are added together at different times, replicating the accumulation of synaptic inputs for the membrane potential. In order to introduce non-linearity into the membrane potential a normalized random number is introduced to this state variable. The proposed architecture uses spike trains as an input much like those in real networks