• DocumentCode
    3509857
  • Title

    A Dual Cache for Performance and Energy Aware Reconfigurable HW

  • Author

    Ramo, E. Pérez ; Resano, J.

  • Author_Institution
    Univ. Complutense de Madrid, Madrid
  • fYear
    2006
  • fDate
    28-30 Aug. 2006
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Nowadays, reconfigurable HW can be used to implement a run-time HW multi-tasking platform where new HW tasks are loaded at run-time using partial reconfiguration, and all the active loaded tasks are executed concurrently. Thus, it is possible to build flexible and adaptable systems that execute optimized HW tasks. These systems are especially suitable for highly dynamic applications. Nevertheless, all this run-time flexibility is not for free. For instance, a dynamic event may trigger the execution of a set of tasks, and loading them generates important execution delays. Moreover, each reconfiguration entails an energy cost. These overheads are often neglected. However, they can severely degrade the systems results, and remove all the advantages that reconfigurable HW introduces. Therefore, developing techniques to minimise these penalties is a critical issue for reconfigurable systems.
  • Keywords
    cache storage; configuration management; multiprogramming; power aware computing; reconfigurable architectures; task analysis; dual cache; energy aware reconfigurable hardware; partial reconfiguration; reconfigurable systems; run-time flexibility; run-time hardware multitasking platform; Computer architecture; Costs; Degradation; Delay; Design optimization; Energy consumption; Field programmable gate arrays; Prefetching; Random access memory; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
  • Conference_Location
    Madrid
  • Print_ISBN
    1-4244-0312-X
  • Type

    conf

  • DOI
    10.1109/FPL.2006.311354
  • Filename
    4101116