Architecture and CAD for FPGA Clock Networks

Scaling of process technologies and innovations in FPGA architecture and CAD are allowing increasingly more sophisticated applications to be implemented on FPGAs. These applications include system-level designs consisting of many subcomponents that use separate clocks. To support a wide range of applications with different clocking schemes, commercial devices have incorporated high-speed, low-skew clock networks that supply multiple clock signals to logic, memory, and arithmetic elements in the FPGA. The design of these programmable clock networks and of the CAD tools that support them is of utmost importance. Not only does the clock network itself dissipate a significant amount of power, since it connects to every latch on the FPGA and toggles every cycle. But, the design of clock network also affects how efficiently the rest of the circuit can be implemented, since it imposed constraints on the CAD tools that map applications onto the FPGA.