DocumentCode
3509921
Title
Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs
Author
Veredas, Francisco-Javier ; Pfleiderer, Hans-Joerg
Author_Institution
Infineon Technol. AG, Munich
fYear
2006
fDate
28-30 Aug. 2006
Firstpage
1
Lastpage
2
Abstract
A conversion flow from a Xilinx Virtex-II Pro FPGA to a Zelix MPGA has been presented. The Zelix MPGA has a predefined regular interconnect. Experimental investigations (Feredas et al.,2006) indicate that the FPGA interconnect has more delay than the proposed MPGA. With better timing closure, studies with the MPGA router shows that a relaxed routing is area prohibitive. Timing integrity seems to be obtainable with high security
Keywords
delays; field programmable gate arrays; integrated circuit interconnections; logic design; reconfigurable architectures; table lookup; timing; FPGA interconnect; LUT-based FPGA; LUT-based MPGA; Xilinx Virtex-II Pro FPGA; Zelix MPGA; area prohibitive; automatic conversion; regular interconnect; timing closure; timing integrity; Communication switching; Costs; Field programmable gate arrays; Integrated circuit interconnections; Microelectronics; Programmable logic arrays; Routing; Switches; Table lookup; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Conference_Location
Madrid
Print_ISBN
1-4244-0312-X
Type
conf
DOI
10.1109/FPL.2006.311358
Filename
4101120
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