Title :
Power Optimization Techniques for SRAM-Based FPGAs
Author :
Mondal, Somsubhra ; Memik, Seda Ogrenci
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL
Abstract :
In this work, the authors aim to improve the power efficiency of FPGAs by proposing two power reduction techniques: the authors present a low-penalty optimization technique to reduce leakage power consumption in FPGA logic blocks by exploiting the variance in LUT utilization across different designs (Mondal and Memik, (2005)), and presents a dual-Vdd-dual-Vt routing architecture to reduce interconnect power consumption by using two levels of Vdd and Vt (Mondal and Memik, (2005))
Keywords :
SRAM chips; circuit optimisation; field programmable gate arrays; power consumption; table lookup; FPGA logic blocks; LUT utilization; SRAM; dual routing architecture; leakage power consumption; low-penalty optimization; power optimization; power reduction techniques; Computer science; Energy consumption; Field programmable gate arrays; Logic arrays; Logic design; Multiplexing; Power engineering and energy; Random access memory; Reliability engineering; Table lookup;
Conference_Titel :
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Conference_Location :
Madrid
Print_ISBN :
1-4244-0312-X
DOI :
10.1109/FPL.2006.311362
