Implementation of Fibonacci test pattern generator for cost effective IC testing

This paper presents a new architecture for test pattern generator that produces the highest fault coverage (FC) with minimum number of pseudo random test vectors. This paper focuses on design and implementation of a 64-bit Fibonacci test pattern generator capable of generating sufficient long test pattern and conducts fault simulation experiments on ISCAS (International Symposium on Circuits and Systems) benchmark circuits. Test pattern generation is one of the more challenging aspects of IC testing. By changing the seed and feedback connection, a set of test vectors is generated for different benchmark circuits. The objective is to produce Test Pattern with good randomness; then fault coverage will be better. Fault simulation is done using FSIM fault simulator.