Title :
Physical layer design of a 1.6 GB/s DRAM bus
Author :
Moncayo, Alfredo ; Hindi, Saad ; Huang, Ching-Chao ; Kollipara, Ravi ; Liaw, Haw-Jyh ; Nguyen, David ; Perino, Don ; Sarfaraz, Ali ; Yuan, Chuck ; Leddige, Michael ; McCall, Jim ; Moua, Xang ; Salmon, Joe
Author_Institution :
Rambus Inc., Mountain View, CA, USA
Abstract :
This paper describes an innovative design and modeling methodology for development of a high performance memory bus with data signaling bandwidth of up to 1.6 gigabytes per second. Data signals operate at 800 megabits per second transfer rate. The clock frequency is 400 MHz and the signal edge transition time is 200 ps. Due to the extremely high frequencies involved, overall system electrical performance must be optimized. By following the methodology outlined in this paper, good correlation was obtained between simulated and measured results
Keywords :
DRAM chips; clocks; digital simulation; integrated circuit design; integrated circuit packaging; optimisation; system buses; 16 Gbit/s; 200 ps; 400 MHz; 800 Mbit/s; DRAM bus; clock frequency; data signaling bandwidth; data signals; design/modeling methodology; memory bus; physical layer design; signal edge transition time; system electrical performance; system electrical performance optimization; transfer rate; Clocks; Connectors; Design methodology; Frequency; Interference constraints; Packaging; Physical layer; Protocols; Random access memory; Signal design;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5597-0
DOI :
10.1109/EPEP.1999.819183
