DocumentCode
3510611
Title
Implementing TreadMarks over Virtual Interface Architecture on Myrinet and gigabit Ethernet: Challenges, design experience, and performance evaluation
Author
Banikazemi, Mohammad ; Liu, Jiuxing ; Panda, Dhabaleswar K. ; Sadayappan, P.
Author_Institution
Dept. of Comput. & Inf. Sci., Ohio State Univ., Columbus, OH, USA
fYear
2001
fDate
3-7 Sept. 2001
Firstpage
167
Lastpage
174
Abstract
In recent years, several user-level communication systems have been developed to eliminate the gap between the performance of networking technologies used in Network Based Computing platforms and that experienced by the applications. The Virtual Interface Architecture (VIA) specification has been recently developed to standardize these communication systems and to make their features available in commercial systems. In this paper, we take on a challenge of developing a communication substrate over VIA such that applications using the popular TreadMarks DSM package can take advantage of the enhanced communication performance of VIA. We discuss various design alternatives, derive the best set of these alternatives and implement them on two enhanced implementations of VIA (M-VIA and Berkeley VIA) on two different networking technologies, Gigabit Ethernet and Myrinet, respectively. We evaluate the performance of our implementation by using several microbenchmarks and applications. We show that the communication and wait times, and therefore the total execution times of different applications can be significantly reduced by using VIA. A reduction in the overall execution time up to 2.05 on an eight node system is demonstrated in comparison with the original UDP implementation. The new implementation also demonstrates better parallel speedup as the system size increases.
Keywords
distributed shared memory systems; local area networks; performance evaluation; Myrinet; TreadMarks; TreadMarks DSM; VIA; Virtual Interface Architecture; gigabit Ethernet; performance; Application software; Communication industry; Computer architecture; Computer networks; Ethernet networks; Hardware; Information science; Middleware; Packaging; Programming environments;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing, 2001. International Conference on
Conference_Location
Valencia, Spain
ISSN
0190-3918
Print_ISBN
0-7695-1257-7
Type
conf
DOI
10.1109/ICPP.2001.952060
Filename
952060
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