Simultaneous switching, noise, and reliability analyses of VLSI core logic

Summary form only given. The rapid advances in process technology have brought many new challenges to IC design. Interconnects are becoming one of the most significant factors in determining the performance of the design. With increased design complexity and reduced feature size, interconnects become more resistive, have more coupling, and cover longer distances on the chip. With the increase in operating frequencies, inductive effects also influence chip performance. Therefore, in order to produce high performance and reliable designs, the interactions in the operation of the devices in terms of the design and the interconnects, including signal lines, power distribution and clock networks, should be correctly modeled and clearly understood early in the design cycle. In this paper, we focus on voltage drop or voltage variations in power and ground buses and delay and crosstalk noise in signal interconnects. We show by theory and by examples that some of the recently published results and some of the techniques followed in industry for dealing with these problems could produce misleading (or erroneous) results. We first show the relationship between switching and timing to reliability and noise analysis, and derive fast input independent techniques to produce tight bounds on worst-case voltage variations and worst-case current flows in the power bus and on crosstalk noise and delay variations in the signal lines. The techniques we develop are also applicable to the estimation of substrate noise and to maximum leakage currents