Title :
On the chicken-and-egg problem of determining the effect of crosstalk on delay in integrated circuits
Author :
Sapatnekar, Sachin S.
Author_Institution :
ECE Dept., Minnesota Univ., Minneapolis, MN, USA
Abstract :
This paper presents an approach to measurement of the effect of crosstalk on the delay of a net using an algorithm whose worst-case complexity is quadratic to the number of nets. The algorithm is amenable to being incorporated into the inner loop of a timing optimizer and is illustrated on a channel router, where it is seen to give improvements of about 20-30% in the average delay in a channel as compared to the worst case
Keywords :
circuit CAD; circuit complexity; circuit optimisation; crosstalk; delays; integrated circuit design; network routing; timing; average channel delay; channel router; crosstalk effect; crosstalk effect measurement; integrated circuit delay; integrated circuits; quadratic worst-case algorithm complexity; timing optimizer; Algorithm design and analysis; Capacitance; Crosstalk; Delay effects; Design optimization; Integrated circuit measurements; Routing; Switches; Timing; Wires;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5597-0
DOI :
10.1109/EPEP.1999.819235
