Design and optimization of nanometric reversible 4 bit numerical comparator

The main idea of reversible logic is to allow the construction of reversible computers - by using components which preserve information content, and can thus potentially be run backwards. Reversible logic gates produce zero power dissipation. So these can be used in nanotechnology, optical computing, quantum computing, DNA computing and low power CMOS design. All of the Boolean functions can be implemented using reversible gates. In this paper we propose a 4-bit nanometric reversible numerical comparator circuit, which makes our proposed design more efficient and optimal. The major constraint in designing the reversible logic circuit is reducing the number of Garbage outputs. Here, we propose a new 3×3 reversible logic gate. In this paper we have used Feyman gate, MHNG gate and proposed Modified TG (MTG) gate to construct the reversible fault tolerant comparator circuit. We show that it is much better and optimized in terms of number of garbage outputs with compared to the existing counterparts.