Title :
High available system control network in the packet transport system
Author :
Kim, Bup-Joong ; Choi, Woo-Young ; Youn, Ji-Wook ; Kim, Hong-Ju ; Lee, Hyun-Jae ; Yu, Jea-Hoon
Author_Institution :
Opt. Network Res. Team, ETRI, Daejeon, South Korea
Abstract :
This paper is about design and buildup of multiprocessor interconnects in the packet transport system. To keep pace with expansion and growth of internet and data communication, constant enhancement and upgrade of packet transport system is required. As network adopts new services like IPTV, VoIP, and VLAN, processing power of packet transport system should be easily and dynamically added to the system for supporting highly compute-power requiring jobs. The processing power of system depends on the number of processors, the clock speed of each processor, efficiency of operation system in data centric processing, proper distribution of system works, and robust and high bandwidth interconnects (system control network) among processors. This paper suggested several methods for the system control networking in the packet transport system and reviewed each method in the view of internal and external expansion of system control network, loop elimination, and redundancy support.
Keywords :
multiprocessor interconnection networks; packet radio networks; high available system control network; loop elimination; multiprocessor interconnection; packet transport system; redundancy support; Ethernet networks; Network topology; Process control; Program processors; Switches; Topology; inter-system control network; packet transport network; system control network; system internal control path;
Conference_Titel :
Optical Internet (COIN), 2010 9th International Conference on
Conference_Location :
Jeju
Print_ISBN :
978-1-4244-7181-2
Electronic_ISBN :
978-1-4244-8221-4
DOI :
10.1109/COIN.2010.5546668