Title :
VLSI implementation of minimum order state-space structures for adaptive digital filters
Author_Institution :
Dept. of Electr. Eng., Florida Atlantic Univ., Boca Raton, FL
Abstract :
The VLSI implementation of a minimum-order structure for a single-input single-output (SISO) digital filter with fixed point arithmetic is investigated. To reduce the number of multipliers, second order parallel structures are proposed. It is shown that the proposed structure presents a good compromise between round off noise, order reduction, number of multipliers and hardware complexity with maximum testability of the circuit
Keywords :
VLSI; adaptive filters; digital filters; fixed point arithmetic; multiplying circuits; state-space methods; VLSI implementation; adaptive digital filters; fixed point arithmetic; hardware complexity; maximum testability; minimum order state-space structures; multipliers; order reduction; round off noise; second order parallel structures; single-input single-output digital filter; Circuit noise; Circuit testing; Digital filters; Eigenvalues and eigenfunctions; Hardware; IIR filters; Noise reduction; Symmetric matrices; Transfer functions; Very large scale integration;
Conference_Titel :
Knowledge-Based Intelligent Information Engineering Systems, 1999. Third International Conference
Conference_Location :
Adelaide, SA
Print_ISBN :
0-7803-5578-4
DOI :
10.1109/KES.1999.820247
