Implementation of DQ domain control in DSP and FPGA

Current control in three-phase voltage source converters (VSC) is usually performed in the dq-coordinate system because of its ability to eliminate steady-state tracking errors. For grid-connected VSCs, such as PWM rectifiers and grid-parallel inverters for integration of renewable energy and energy storage devices, a phase-locked loop (PLL) is commonly used to synthesize a set of harmonic-free voltages synchronized to the grid voltages for transformation between the dq and the abc coordinate systems. The multitude of control functions in large systems, such as wind turbines, necessitate the use of multiple digital control devices. In such cases, the PLL output has to be transferred among different devices. To reduce the bandwidth requirements and noise susceptibility of such signal transfer, this paper presents a PLL implementation method that distributes the PLL function into different devices. Instead of transferring directly the synthesized grid voltage angle, the synthesized grid frequency, which has much lower signal bandwidth, is communicated. A binary reset signal is used to eliminate the difference between initial values of the distributed integrators that convert locally frequency into reference angle. An experimental system consisting of a three-phase VSC, a TMS320F28335 DSP, and an Altera DE2 board with a Cyclone II EP2C35 field programmable gate array (FPGA) is used to demonstrate the proposed concept.