Title :
A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software
Author :
Karthikeyan, Muthu ; Fox, Stephen ; Cote, William ; Yeric, Greg ; Hall, Michael ; Garcia, John ; Mitchell, Barry ; Wolf, Eric ; Agarwal, Suresh
Author_Institution :
IBM Syst. & Technol. Group, Hopewell Junction, NY, USA
Abstract :
This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65nm random and systematic yield. This infrastructure consists of a 4Mb addressable-array test circuit with > 8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.
Keywords :
integrated circuit testing; integrated circuit yield; 65 nm; addressable-array test circuit; integrated analysis software; test structures; yield ramp infrastructure; Application software; Automatic testing; Character generation; Circuit testing; Cost function; Electronics industry; Optical arrays; Software testing; Topology; Vehicles;
Conference_Titel :
Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on
Print_ISBN :
1-4244-0167-4
DOI :
10.1109/ICMTS.2006.1614284
