Low-power application-specific processor for FFT computations

Author

Pitkänen, Teemu ; Takala, Jarmo

Author_Institution

Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere

fYear

2009

fDate

19-24 April 2009

Firstpage

593

Lastpage

596

Abstract

In this paper, we describe a processor architecture tailored for radix-4 and mixed-radix FFT algorithms, which have lower arithmetic complexity than radix-2 algorithms. The processor is based on transport triggered architecture and several optimizations have been used to improve the energy-efficiency. The processor has been synthesized on a 130 nm standard cell technology and analysis show that a programmable solution can possess energy-efficiency comparable to a fixed-function ASIC.

Keywords

application specific integrated circuits; computational complexity; fast Fourier transforms; low-power electronics; microprocessor chips; arithmetic complexity; energy-efficiency; fast Fourier transform; fixed-function ASIC; low-power application-specific processor; mixed-radix FFT algorithms; processor architecture; radix-4 algorithms; standard cell technology; transport triggered architecture; Application specific integrated circuits; Application specific processors; Computer architecture; Digital arithmetic; Discrete Fourier transforms; Energy efficiency; Integrated circuit synthesis; Integrated circuit technology; Signal processing algorithms; Signal synthesis; Application specific integrated circuits; Digital signal processors; Discrete Fourier transforms; Parallel architectures;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing, 2009. ICASSP 2009. IEEE International Conference on

Conference_Location

Taipei

ISSN

1520-6149

Print_ISBN

978-1-4244-2353-8

Electronic_ISBN

1520-6149

Type

conf

DOI

10.1109/ICASSP.2009.4959653

Filename

4959653