A parallel architecture for 3GPP2/UMB turbo interleavers

In this paper, an efficient architecture for a parallel pruned turbo interleaver for 3GPP2/UMB physical layer standard is presented. Turbo interleaving in UMB turbo codes is based on filling a 2D array row by row, interleaving each row using a linear congruential sequence, bit-reversing the order of the rows, and then reading the interleaved addresses column by column. Pruning creates a serial bottleneck since the interleaved address of a linear address x is a function of the number of pruned addresses up to x. An architecture based on the parallel lookahead pruned interleaving algorithm proposed in is presented. The algorithm breaks this dependency and interleaves any address in O(log² x) steps by enabling a parallel turbo interleaver design with a desired degree of parallelism. The architecture can be implemented efficiently in hardware using basic arithmetic building blocks.