Design for testability in nanometer technologies; searching for quality

Author

Williams, T.W. ; Kapur, Rohit

Author_Institution

Synopsys Inc., Boulder, CO, USA

fYear

2000

fDate

2000

Firstpage

167

Lastpage

171

Abstract

Today´s technology allows for the creation of designs that are stressing methodologies from a time to market point of view. The industry is in a transition period where the methodologies and tools are changing to allow for reusing designs as cores. With a promise of large capacity, the miniaturization of the devices brings along new problems and changes the focus of Design for Testability (DFT) and for all the tools used in the successful manufacturing of the design. In this paper, the impact of nanometer technology on the issues associated with testing of system-on-chip (SOC) designs is discussed

Keywords

VLSI; application specific integrated circuits; design for testability; integrated circuit design; integrated circuit testing; nanotechnology; ASIC; DFT; SOC designs; design for testability; nanometer technologies; system on chip designs; Circuit testing; Delay effects; Delay estimation; Design for testability; Electromagnetic coupling; Logic testing; Semiconductor device manufacture; Time to market; Timing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7695-0525-2

Type

conf

DOI

10.1109/ISQED.2000.838870

Filename

838870