Synthesis experiments and performance metrics for evaluating the quality of IP blocks and megacells

A complete quantitative evaluation of the quality of more than one hundred implementations of SPARC processor core and its related circuitry, synthesized from VHDL descriptions, is presented in this paper as a demonstration example for selecting benchmark circuits, synthesis experiments with different tools and technologies, and performance metrics, for evaluating the quality of IP blocks and megacells. The methodology of the experiments conducted for these circuits can be applied to a wide range of other benchmark candidate circuits. The synthesis experiments are designed to fully explore the synthesis space and to analyze the impact of every synthesis step on the final design quality obtained