A flexible network-on-chip simulator for early design space exploration

Author

Grecu, Cristian ; Ivanov, André ; Saleh, Resve ; Rusu, Claudia ; Anghel, Lorena ; Pande, Partha P. ; Nuca, Vasile

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC

fYear

2008

fDate

15-15 Oct. 2008

Firstpage

33

Lastpage

36

Abstract

The communication requirements of large multi-core systems are convened by on-chip communication fabrics generally referred to as networks-on-chip (NoC). We have designed a simulation environment that allows early exploration of the performance and cost parameters of network-on-chip communication architectures, which is able to handle arbitrary topologies and routing schemes. The simulator implements a flit-level message-passing mechanism and supports application data specified as input trace files or generated at run-time by synthetic traffic generators.

Keywords

circuit simulation; electronic engineering computing; message passing; network-on-chip; telecommunication network routing; flexible network-on-chip simulator; flit-level message-passing mechanism; input trace files; network-on-chip communication architectures; on-chip communication fabrics; routing schemes; synthetic traffic generators; Costs; Fabrics; Network topology; Network-on-a-chip; Routing; Runtime; Space exploration; System-on-a-chip; Telecommunication traffic; Traffic control; Network-on-chip; performance; simulator;

fLanguage

English

Publisher

ieee

Conference_Titel

Microsystems and Nanoelectronics Research Conference, 2008. MNRC 2008. 1st

Conference_Location

Ottawa, Ont.

Print_ISBN

978-1-4244-2920-2

Electronic_ISBN

978-1-4244-2921-9

Type

conf

DOI

10.1109/MNRC.2008.4683371

Filename

4683371