DocumentCode
3514054
Title
Assertion checkers - enablers of quality design
Author
Boulé, Marc ; Zilic, Zeljko
Author_Institution
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC
fYear
2008
fDate
15-15 Oct. 2008
Firstpage
97
Lastpage
100
Abstract
This paper outlines the MBAC tool for the generation of assertion checkers in hardware. We begin with a high-level presentation of the automated compilation of assertions into checkers, and proceed to overview the multitude of applications of resource-efficient circuit-level checkers in the field of logic design and verification. A summary of experimental results is also given to show the current state of the MBAC tool, compared to the best known checker generator from IBM.
Keywords
design for quality; high level languages; logic design; MBAC tool; assertion checkers; automated compilation; circuit-level checkers; hardware; logic design; quality design; Application software; Circuit faults; Circuit simulation; Debugging; Electronic design automation and methodology; Hardware; Logic; Observability; Signal design; Specification languages; Assertion; Checker; Debug; Design; Verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Microsystems and Nanoelectronics Research Conference, 2008. MNRC 2008. 1st
Conference_Location
Ottawa, Ont.
Print_ISBN
978-1-4244-2920-2
Electronic_ISBN
978-1-4244-2921-9
Type
conf
DOI
10.1109/MNRC.2008.4683387
Filename
4683387
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