DocumentCode :
3514227
Title :
Performance optimization of room temperature Deflection Transistors through modified geometry
Author :
Kaushal, Vikas ; Diduck, Quentin ; Margala, Martin
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Massachusetts Lowell, Lowell, MA
fYear :
2008
fDate :
15-15 Oct. 2008
Firstpage :
145
Lastpage :
148
Abstract :
In this paper, the current status of the ballistic deflection transistor (BDT) project is described. The project focuses on a development of a new class of devices based on the steering of the electron flux and the ballistic deflection effect. The results of the latest experiments show significant current response improvement through optimized geometry modifications.
Keywords :
ballistic transport; transistors; ballistic deflection effect; ballistic deflection transistor; electron flux steering; modified geometry; performance optimization; room temperature deflection transistors; Electrons; Geometry; Lithography; Logic; Optimization; Particle scattering; Substrates; Temperature; Transconductance; Voltage; Ballistic Transport; Current Steering; Deflection Transistors; Diffusive Transport;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microsystems and Nanoelectronics Research Conference, 2008. MNRC 2008. 1st
Conference_Location :
Ottawa, Ont.
Print_ISBN :
978-1-4244-2920-2
Electronic_ISBN :
978-1-4244-2921-9
Type :
conf
DOI :
10.1109/MNRC.2008.4683399
Filename :
4683399
Link To Document :
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