Title :
An integrated reset / pulse pile-up rejection circuit for pixel readout ASIC´s
Author :
Bastia, P. ; Bertuccio, G. ; Borghetti, F. ; Caccia, S. ; Ferragina, V. ; Ferrari, F. ; Maiocchi, D. ; Malcovati, P. ; Martin, D. ; Pullia, A. ; Ratti, N.
Author_Institution :
Alenia Spazio S.p.A., Vimodrone, Italy
Abstract :
We present a compact and low power integrated circuit designed to control the reset and performs the pulse pile-up rejection in multi-channel spectroscopic-grade ASIC´s. The circuit has been implemented in 0.35 mum CMOS technology with an area of 60times80 mum2 and null static power consumption. These features makes this circuit suitable to be embedded into the front-end readout cells for spectroscopy/imaging X and gamma ray pixel detectors.
Keywords :
CMOS integrated circuits; X-ray detection; X-ray imaging; X-ray spectrometers; application specific integrated circuits; gamma-ray detection; gamma-ray spectrometers; nuclear electronics; position sensitive particle detectors; readout electronics; 0.35 mum; CMOS technology; X-ray imaging detectors; compact integrated circuit; front-end readout cells; gamma-ray imaging detectors; integrated reset-pulse pile-up rejection circuit; low power integrated circuit; multichannel spectroscopic-grade ASIC; null static power consumption; pixel detectors; pixel readout ASIC; spectroscopic detectors; CMOS technology; Energy consumption; Gamma ray detection; Gamma ray detectors; Integrated circuit technology; Optical imaging; Pixel; Power integrated circuits; Pulse circuits; Spectroscopy;
Conference_Titel :
Nuclear Science Symposium Conference Record, 2004 IEEE
Conference_Location :
Rome
Print_ISBN :
0-7803-8700-7
Electronic_ISBN :
1082-3654
DOI :
10.1109/NSSMIC.2004.1462505
