DocumentCode :
3514765
Title :
Optimization of the drive circuit for enhancement mode power GaN FETs in DC-DC converters
Author :
Xi, Youhao ; Chen, Min ; Nielson, Kim ; Bell, Robert
Author_Institution :
Texas Instrum., Phoenix, AZ, USA
fYear :
2012
fDate :
5-9 Feb. 2012
Firstpage :
2467
Lastpage :
2471
Abstract :
This paper discusses the practical concerns and optimization of the drive circuit for enhancement mode Gallium-Nitride (GaN) power transistors in dc-dc converters. The GaN FET´s 6.0V absolute maximum gate voltage rating and ultra low threshold voltage impose strict constrains on the drive circuit. It is critical to achieve precise gate voltage limit, realize a low impedance gate signal path, and meet the stringent noise immunity requirements by optimizing the gate drive circuit. Prototype converters were built and experimental results are presented as proof of concept.
Keywords :
DC-DC power convertors; III-V semiconductors; driver circuits; gallium compounds; power field effect transistors; wide band gap semiconductors; DC-DC converters; GaN; drive circuit optimization; enhancement mode power gallium nitride FET; gate signal path; gate voltage rating; noise immunity requirements; threshold voltage; voltage 6.0 V; Capacitors; FETs; Gallium nitride; Layout; Logic gates; MOSFET circuits; Optimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4577-1215-9
Electronic_ISBN :
978-1-4577-1214-2
Type :
conf
DOI :
10.1109/APEC.2012.6166168
Filename :
6166168
Link To Document :
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