Title :
Pipelining considerations for an FPGA case
Author :
Cadenas, Oswaldo ; Megson, Graham
Author_Institution :
Dept. of Comput. Sci., Reading Univ., UK
Abstract :
This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case
Keywords :
field programmable gate arrays; logic design; timing; FPGA; asynchronous worst-case data completion; bundle-data pipeline; doubly-latched asynchronous pipeline; pipelining considerations; semi-synchronous pipeline scheme; single-pulse pipeline; systolic circuit; timing considerations; Circuits; Clocks; Computer aided software engineering; Computer science; Delay; Field programmable gate arrays; Pipeline processing; Proposals; Quantization; Timing;
Conference_Titel :
Digital Systems Design, 2001. Proceedings. Euromicro Symposium on
Conference_Location :
Warsaw
Print_ISBN :
0-7695-1239-9
DOI :
10.1109/DSD.2001.952298