Reconfigurable computing in the heterogeneous manycore Era

Field Programmable Gate Array (FPGA) densities have continued to track Moore´s law and now contain sufficient gates, block RAMs (BRAMs), and diffused logic to support a complete Multiprocessor System on Programmable Chip (MPSoC). To exploit this new capability, Xilinx is encouraging designers to target the processor instead of the transistor as the smallest design quantum [4]. Interestingly, this viewpoint is converging with similar viewpoints in the commercial, general-purpose computing community, which is also promoting performance gains through scalable numbers of parallel processors within a manycore chip. In both domains, architectures continue to transition towards systems with heterogeneous mixes of processors to match workload requirements composed of both SIMD (data-level), and MIMD (thread-level) parallelism.