Nano-scaled functional layers for current and heat transport in electronics packaging

The amount of information capable of being stored on a computer chip doubles every two years as stated first by Gordon Moore in 1965. Electronics packaging technology has to adopt the resulting requirements of this tremendous development of the microelectronic industry. In view of future applications it is necessary to establish new interconnect materials for high-density electronics packaging because common materials are facing physical barriers and fail to meet the requirements of nano-scale miniaturisation. These requirements will be steady miniaturisation of the electronic devices, higher current density per device, pitches down to 20 mum and higher thermal dissipation loss. Current joining elements cannot meet these requirements. For common joining element materials there are also limitations with regard to their thermomechanical behaviour. Downscaling of traditional solder bump materials to lower pitch cannot satisfy the reliability requirement [1]. For example, lead and lead-free solders typically fail when scaled down to less than 100 micron pitch due to poor fatigue resistance. On the other hand compliant interconnections do not meet the high frequency electrical requirements. Consequently, there is a need for new joining materials in electronics packaging. Carbon nanotubes (CNTs) are promising candidates for functional layers for packaging in the nanometre scale because of their superior mechanical, thermal and electrical properties. The reproducibility and the performance of such structures for thermal and electrical transport on common packaging substrates are not sufficiently known and were investigated by our groups. Latest results concerning the preparation of CNT films and their structural and functional properties are described in the present paper. Using a ldquobottom uprdquo approach the CNTs are grown with a defined wall structure on a catalyst layer by chemical vapour deposition (CVD). The catalyst layer is a nano-structured deposit on a Si wafe- - r formed by a self assembly mechanism. The nano-scaled structuring is the most important requirement for manufacturing CNTs with defined properties. Unlike state-of-the-art methods a layer of a conducting material is deposited on the Si surface as finish. This conducting layer could be the basis for the following die bonding process transferring the CNT layer on common packaging substrates. The application potential is exemplarily shown.