Title :
A 3.1 to 4.85GHz differential CMOS low noise amplifier for lower band of UWB applications
Author :
Vaithianathan, V. ; Raja, J. ; Kavya, R. ; Anuradha, N.
Author_Institution :
Dept. of ECE, SSN Coll. of Eng., Kalavakkam, India
Abstract :
An UWB LNA that employs the differential topology with a cascode common gate stage as the core amplifier is proposed for lower band of ultra wideband (UWB) applications. This differential LNA is designed to obtain a power gain greater than 15dB and a noise figure less than 1dB. The common gate stage at the input offers input matching and the output matching is attained using a common drain buffer amplifier. The input and output matching are aimed at less than -10dB while the reverse isolation is well below -40dB. The LNA ensures better linearity with an in-band IIP3 of -3dBm. The LNA is allowed to consume a very low power of 4mW at an operating voltage of 1V. The performance analysis of this proposed LNA is carried out using Agilent´s ADS 2008 simulator employing 90nm CMOS technology.
Keywords :
CMOS integrated circuits; differential amplifiers; low noise amplifiers; Agilent´s ADS 2008 simulator; UWB LNA; cascode common gate stage; differential CMOS low noise amplifier; differential topology; frequency 3.1 GHz to 4.85 GHz; power 4 mW; size 90 nm; voltage 1 V; Broadband amplifiers; CMOS technology; Differential amplifiers; Impedance matching; Linearity; Low-noise amplifiers; Noise figure; Topology; Ultra wideband technology; Voltage; Input Third Order Intercept Point; Noise Figure; Power Gain;
Conference_Titel :
Wireless Communication and Sensor Computing, 2010. ICWCSC 2010. International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4244-5136-4
Electronic_ISBN :
978-1-4244-5137-1
DOI :
10.1109/ICWCSC.2010.5415894
