Title :
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
Author :
Raghav, Shivani ; Ruggiero, Martino ; Atienza, David ; Pinto, Christian ; Marongiu, Andrea ; Benini, Luca
Author_Institution :
ESL, EPFL, Lausanne, Switzerland
fDate :
June 28 2010-July 2 2010
Abstract :
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.
Keywords :
computer graphic equipment; coprocessors; instruction sets; parallel architectures; performance evaluation; GPGPUs; parallel architectures; parallel processing; parallel systems; performance evaluation; scalable instruction set simulator; thousand-core architectures; virtual platforms; Computational modeling; Context; Decoding; Kernel; Multicore processing; Registers; CUDA; GPGPU; ISS; manycore;
Conference_Titel :
High Performance Computing and Simulation (HPCS), 2010 International Conference on
Conference_Location :
Caen
Print_ISBN :
978-1-4244-6827-0
DOI :
10.1109/HPCS.2010.5547092
