DocumentCode
3515949
Title
A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture
Author
Jakob, C. ; Schwarzbacher, A. Th ; Hoppe, B. ; Peters, R.
Author_Institution
Sch. of Electron. & Commun. Eng., Dublin Inst. of Technol., Dublin, Ireland
fYear
2007
fDate
29-31 Aug. 2007
Firstpage
35
Lastpage
42
Abstract
Digital correlation techniques are used in photon correlation spectroscopy (PCS) experiments to gain information about the diffusion coefficient and thereby the size and distribution of submicron particle structures in fluid media. A new multichannel single chip correlator architecture has been developed, implemented on a FPGA device as a HW/SW partitioned system. A fast hardware front-end combined with a highly optimised, hardware accelerated softcore processor allows the simultaneous processing of up to 32 input channels, each with a time dynamic range 1013. This paper outlines the fundamental algorithmic concepts, the actual correlator implementation as well as the HW/SW design consideration to find an optimal trade-off between system resources and application requirements.
Keywords
correlation methods; field programmable gate arrays; hardware-software codesign; logic partitioning; FPGA device; HW/SW design; HW/SW partitioned system; digital correlation techniques; digital real-time mutichannel correlator architecture; hardware accelerated softcore processor; multichannel single chip correlator architecture; Computer architecture; Correlators; Dynamic range; Field programmable gate arrays; Fluctuations; Hardware; Light scattering; Solvents; Spectroscopy; Viscosity;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location
Lubeck
Print_ISBN
978-0-7695-2978-3
Type
conf
DOI
10.1109/DSD.2007.4341447
Filename
4341447
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