A resource optimized Processor Core for FPGA based SoCs

Author

Hempel, Gerald ; Hochberger, Christian

Author_Institution

Dept. for Embedded Syst., Dresden Univ. of Technol., Dresden, Germany

fYear

2007

fDate

29-31 Aug. 2007

Firstpage

51

Lastpage

58

Abstract

Modern FPGAs have become so affordable that they can be used to substitute ASICs in mass produced devices. Typically, the term configurable system on a chip (CSoC) is used for this kind of usage. A key component in such a CSoC is the processor core. Currently, several cores are available for FPGAs. 32 bit processors like MicroBlaze, NIOS 2 or OpenRisc require a lot of resources, whereas very small solutions like PicoBlaze or Lattice Mico8 are not capable of running reasonably complex software. Thus, there is a gap between these two extremes, which we want to fill with our development SpartanMC. This contribution describes its design objectives, architecture, tools, peripherals and compares it to other well known processor cores.

Keywords

field programmable gate arrays; integrated circuit design; logic design; system-on-chip; FPGA based SoC design; SpartanMC processor core; configurable system on a chip; resource optimized processor core; Application software; Computer architecture; Costs; Embedded system; Field programmable gate arrays; Heart; Lattices; Logic devices; Microcontrollers; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on

Conference_Location

Lubeck

Print_ISBN

978-0-7695-2978-3

Type

conf

DOI

10.1109/DSD.2007.4341449

Filename

4341449