An Implementation of an Address Generator Using Hash Memories

Author

Sasao, T. ; Matsuura, Munehiro

Author_Institution

Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan

fYear

2007

fDate

29-31 Aug. 2007

Firstpage

69

Lastpage

76

Abstract

An address generator produces a unique address from 1 to k for the input that matches to one of k registered vectors, and produces 0 for other inputs. This paper presents the super hybrid method to design an address generator. The hash memories realize about 96% of the registered vectors, while the reconfigurable PLA realizes the remaining 4% of the registered vectors. With the super hybrid method, we can implement up to 20 times more registered vectors than the conventional method that uses only logic elements of an FPGA. Experimental results using lists of English words show that the usefulness of the approach.

Keywords

field programmable gate arrays; flash memories; logic design; vectors; FPGA logic elements; address generation function; address generator; hash memories; hash-based design; k distinct binary vectors; k registered vectors; programmable logic array; reconfigurable PLA; super hybrid method; Circuits; Computer science; Design methodology; Field programmable gate arrays; Hybrid power systems; Impedance matching; Information filtering; Programmable logic arrays; Reconfigurable logic; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on

Conference_Location

Lubeck

Print_ISBN

978-0-7695-2978-3

Type

conf

DOI

10.1109/DSD.2007.4341452

Filename

4341452