DocumentCode :
3516294
Title :
On Complexity of Internal and External Equivalence Checking
Author :
Goldberg, Eugene ; Gulati, Kanupriya
Author_Institution :
Cadence Design Syst., Texas A&M Univ., College Station, TX, USA
fYear :
2007
fDate :
29-31 Aug. 2007
Firstpage :
197
Lastpage :
206
Abstract :
We compare the complexity of "internal" and "external" equivalence checking. The former is meant for proving the correctness of a synthesis transformation by which circuit N2 is obtained from circuit N1. The latter is meant for proving that circuits N1 and N2 are functionally equivalent without making any explicit assumptions about the origin of N1 and N2. We describe logic synthesis procedures that can produce a circuit N2 whose equivalence with the original circuit N1, most likely, can not be efficiently proved by an external equivalence checker. On the other hand, there are internal equivalence checking procedures that easily prove that N1 and N2 are equivalent. We give experimental data showing that these logic synthesis procedures are not a mathematical curiosity but indeed can be used as a powerful method of logic optimization.
Keywords :
combinational circuits; logic design; optimisation; combinational circuits; equivalence checking; logic optimization; logic synthesis procedures; logic transformation; synthesis transformation; toggle equivalence; Binary decision diagrams; Circuit synthesis; Circuit testing; Combinational circuits; Logic circuits; Optimization methods; Registers; Scalability; Sequential circuits; Tellurium;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location :
Lubeck
Print_ISBN :
978-0-7695-2978-3
Type :
conf
DOI :
10.1109/DSD.2007.4341469
Filename :
4341469
Link To Document :
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