• DocumentCode
    3516320
  • Title

    RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip

  • Author

    Paya-Vaya, Guillermo ; Martín-Langerwerf, Javier ; Pirsch, Peter

  • Author_Institution
    Inst. of Microelectron. Syst., Leibniz Univ. of Hannover, Hannover, Germany
  • fYear
    2007
  • fDate
    29-31 Aug. 2007
  • Firstpage
    215
  • Lastpage
    221
  • Abstract
    This paper describes a case study in a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The goal of the presented methodology is to speed up and improve the verification flow of a multiprocessor system that will finally be implemented as an ASIC. The case study consists of a 64-bit compatible AMBA AHB system bus which connects up to 14 32-Bit RISC processors to a host interface. A typical parallel computing application has been implemented for the parameterized multiprocessor system. The employed FPGA emulation environment increases by up to 200 the simulation frequency of the global system on a workstation (2.2 GHz AMD Dual Opteron with 8 GB RAM). Moreover a standalone emulation can be performed at the maximum achievable frequency (65 MHz).
  • Keywords
    field programmable gate arrays; integrated circuit design; multimedia computing; multiprocessing systems; parallel architectures; reduced instruction set computing; software prototyping; system buses; system-on-chip; AMBA AHB system bus; ASIC; FPGA emulation environment; RAPANUI; RISC processors; design verification; frequency 65 MHz; multimedia applications; multiprocessor architectures; multiprocessor system-on-chip; parallel computing application; parameterized multiprocessor system; rapid prototyping-based design framework; Application specific integrated circuits; Computational modeling; Emulation; Field programmable gate arrays; Frequency; Multiprocessing systems; Parallel processing; Prototypes; Reduced instruction set computing; System buses;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
  • Conference_Location
    Lubeck
  • Print_ISBN
    978-0-7695-2978-3
  • Type

    conf

  • DOI
    10.1109/DSD.2007.4341471
  • Filename
    4341471