Nano-technology aware investigations on fault-masking techniques in the presence of high fault probabilities

Nano-architectures are promising alternatives for current CMOS technology, which is facing serious challenges for further down-scaling. However, high failure rates — compared to the conventional CMOS process — lead to multiple faults during lifetime operation of nano-architectures. In this paper, we investigate the outcome of traditional fault-masking techniques in the presence of high fault probabilities. Redundant codes and circuit structures are evaluated in a generic way, using stochastic methods. The original goal was to provide a means to decide, under which conditions, which fault-masking techniques are worthwhile. Our results, however, suggest, that these techniques require extremely low fault rates and/or cause extraordinarily high additional cost.