Title :
GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors
Author :
Puttmann, Christoph ; Niemann, Jörg-Christian ; Porrmann, Mario ; Rückert, Ulrich
Author_Institution :
Heinz Nixdorf Inst., Univ. of Paderborn, Paderborn, Germany
Abstract :
Due to the technological progress in the semiconductor industry, more and more components can be integrated on a single die forming a complex System-on-Chip. For enabling an efficient interaction between the various building blocks of today´s SoCs, efficient communication structures become more and more essential. In this paper, we present the GigaNoC, a hierarchical Network-on-Chip that is especially suitable for scalable Chip-Multiprocessor architectures. The GigaNoC approach features a packet-switched wormhole routing on-chip network that provides the backbone of our multiprocessor architecture. In order to meet bandwidth requirements of different application domains, our Network-on-Chip is easily scalable and parameterizable in various aspects. This work highlights the communication protocol and shows a performance evaluation for different congestion scenarios. Furthermore, we present an FPGA-based prototypical realization and introduce a debugging and verification environment. Finally, implementation results for a standard cell technology are discussed.
Keywords :
field programmable gate arrays; network routing; network-on-chip; performance evaluation; FPGA; GigaNoC; field programmable gate arrays; multiprocessor architecture; network-on-chip; packet-switched wormhole routing on-chip network; performance evaluation; scalable chip-multiprocessors; standard cell technology; Communication switching; Computer architecture; Debugging; Hardware; Network-on-a-chip; Prototypes; Routing; Spine; Switches; System-on-a-chip;
Conference_Titel :
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location :
Lubeck
Print_ISBN :
978-0-7695-2978-3
DOI :
10.1109/DSD.2007.4341514