Integrating design, manufacture and test using capability measures

Successful electronic products rely on a combination of good design, appropriate manufacturing processes and effective test and inspection. In order to achieve all of these within a highly cost constrained environment requires that sufficient, but not excessive, resources are applied to each area. One problem which makes it difficult to balance the allocation of resources is that different measures of performance are used in each context. In the design domain, the objectives are typically design centring, robust design, part count reduction or component cost reduction. Objectives in manufacturing processes are typically yield maximisation, process capability, defect reduction etc. In the test arena, the aim is typically to maximise test coverage and minimising test/inspection times. Given this plethora of different measures of performance, it is difficult to assess trade-offs between different domains and decide appropriate resource allocations.In order to address this problem we have proposed a unified measure of capability across the design/manufacture/test spectrum. This is based on the process capability measure Cpk which has been adapted to measure functional capability: the ability of a design to meet its performance specification in the presence of component parameter variations, and to test capability: the ability of test/inspection processes to correctly identify defects without erroneously indicating defects which are not present. These capability measures may be related to the costs arising from defects through scrap, rework and warranty returns through a failure modes and effects analysis (FMEA) and a quality cost mapping process. This makes it possible to quantify and compare the cost consequences of design decisions. This unifying analysis methodology is termed electronic conformability analysis (eCA). The paper introduces the eCA methodology, explains the functional, manufacture and test capability measures and shows how these may be related to qualit- - y cost. The application of the methodology to a simple example circuit is presented.