DocumentCode :
3517188
Title :
Hybrid BIST Optimization Using Reseeding and Test Set Compaction
Author :
Jervan, Gert ; Orasson, Elmet ; Kruus, Helena ; Ubar, Raimund
Author_Institution :
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia
fYear :
2007
fDate :
29-31 Aug. 2007
Firstpage :
596
Lastpage :
603
Abstract :
Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper we are concentrating on one possible extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and to reduce test time. We will propose a novel method for hybrid BIST optimization, based on reseeding and test set compaction. The objective is to minimize the test time at given test memory constraints, without losing test quality. We will compare the proposed method with hybrid BIST methods developed earlier and analyze its suitability for testing core-based systems.
Keywords :
automatic test pattern generation; built-in self test; optimisation; built-in self-test optimization; fault coverage; linear feedback shift registers; pseudorandom testing; reseeding; test set compaction; test set generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Fault detection; Linear feedback shift registers; System testing; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location :
Lubeck
Print_ISBN :
978-0-7695-2978-3
Type :
conf
DOI :
10.1109/DSD.2007.4341529
Filename :
4341529
Link To Document :
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