DocumentCode
3517247
Title
An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits
Author
Moghaddam, Elham K. ; Hessabi, Shaahin
Author_Institution
Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
fYear
2007
fDate
29-31 Aug. 2007
Firstpage
619
Lastpage
625
Abstract
This paper presents a simulation-based study of the stuck-open fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting stuck-open faults in these logic families. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented.
Keywords
CMOS logic circuits; built-in self test; fault diagnosis; logic testing; CMOS logic circuits; built-in self-test; on-line BIST technique; robust on-line testing; stuck-open fault detection; Built-in self-test; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Delay; Electrical fault detection; Fault detection; Logic testing; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location
Lubeck
Print_ISBN
978-0-7695-2978-3
Type
conf
DOI
10.1109/DSD.2007.4341532
Filename
4341532
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