DocumentCode
3517322
Title
An Efficient BIST Scheme for Non-Restoring Array Dividers
Author
Vergos, H.T.
Author_Institution
Comput. Eng. & Inf. Dept., Univ. of Patras, Patras, Greece
fYear
2007
fDate
29-31 Aug. 2007
Firstpage
664
Lastpage
667
Abstract
A new effective built-in self-test (BIST) scheme for non- restoring array dividers (NADs) is proposed, that offers more than 99% cell fault coverage in all NADs of practical use. Moreover, it can be implemented in small hardware and can apply all its test vectors within 128 clock cycles. A version of the proposed scheme for power critical applications is also exploited.
Keywords
built-in self test; logic arrays; logic testing; BIST scheme; NAD; built-in self-test scheme; clock cycles; nonrestoring array dividers; test vectors; Adders; Automatic testing; Built-in self-test; Circuit faults; Clocks; Delay; Design for testability; Hardware; Informatics; Power generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location
Lubeck
Print_ISBN
978-0-7695-2978-3
Type
conf
DOI
10.1109/DSD.2007.4341538
Filename
4341538
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