Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application

This study presents vertical Si-nanowire (SiNW) gate all-around (GAA) non-volatile memory with channel diameter down to 20nm. The junction-less devices with SiN trap layer is found to have comparable memory characteristics (3.2V in 1ms P/E at +15V/-16V) to the junction-based cell. Despite of that, the absence of junctions reduces the process complexity and makes vertical SiNW a suitable platform for multi-level stacked ultra high density memory application.