Title :
Low-voltage scaling limitations for nano-scale CMOS LSIs
Author_Institution :
Res. Lab., Hitachi, Ltd., Tokyo
Abstract :
LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (Vmin) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD- SOIs and/or high-ft metal gates) that can reduce Vmin variations.
Keywords :
CMOS logic circuits; CMOS memory circuits; DRAM chips; SRAM chips; large scale integration; nanoelectronics; DRAM sense amplifiers; MOSFET; SRAM cells; logic gates; low-voltage scaling limitations; nanoscale CMOS LSI; threshold voltage; CMOS logic circuits; Degradation; Logic arrays; Logic circuits; Logic devices; Logic gates; MOSFETs; Random access memory; Read-write memory; Threshold voltage;
Conference_Titel :
Ultimate Integration of Silicon, 2008. ULIS 2008. 9th International Conference on
Conference_Location :
Udine
Print_ISBN :
978-1-4244-1729-2
Electronic_ISBN :
978-1-4244-1730-8
DOI :
10.1109/ULIS.2008.4527128
