• DocumentCode
    3517799
  • Title

    Low-voltage scaling limitations for nano-scale CMOS LSIs

  • Author

    Itoh, Kiyoo

  • Author_Institution
    Res. Lab., Hitachi, Ltd., Tokyo
  • fYear
    2008
  • fDate
    12-14 March 2008
  • Firstpage
    3
  • Lastpage
    6
  • Abstract
    LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (Vmin) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD- SOIs and/or high-ft metal gates) that can reduce Vmin variations.
  • Keywords
    CMOS logic circuits; CMOS memory circuits; DRAM chips; SRAM chips; large scale integration; nanoelectronics; DRAM sense amplifiers; MOSFET; SRAM cells; logic gates; low-voltage scaling limitations; nanoscale CMOS LSI; threshold voltage; CMOS logic circuits; Degradation; Logic arrays; Logic circuits; Logic devices; Logic gates; MOSFETs; Random access memory; Read-write memory; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Ultimate Integration of Silicon, 2008. ULIS 2008. 9th International Conference on
  • Conference_Location
    Udine
  • Print_ISBN
    978-1-4244-1729-2
  • Electronic_ISBN
    978-1-4244-1730-8
  • Type

    conf

  • DOI
    10.1109/ULIS.2008.4527128
  • Filename
    4527128
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3517799