Author :
Coronel, P. ; Arnaud, F. ; Harrison, S. ; Wacquez, R. ; Bustos, J. ; Pouydebasque, A. ; Borot, B. ; Gallon, C. ; Fenouillet-Béranger, C. ; Pain, L. ; Delille, D. ; Bourdon, H. ; Borel, S. ; Arnal, V. ; Ferreira, P. ; Lenoble, D. ; Skotnicki, T.
Abstract :
This paper demonstrates the possibility to use a bottom-up front-end (FE) architecture for sub-32 nm CMOS nodes with a new 3D approach in front-end flow. This architecture based on the so called FRETCH (film replacement etching through contact hole) solution [1] is compatible to adapt a specific device before or after electrical test. To address the full 3D in FE concept of buried integration will be proposed by using e-beam and HSQ material. Finally a novel integration scheme fully compatible with conventional bulk flow with one mask will be depicted allowing a self assembly structure and reducing significantly the process variability.
Keywords :
CMOS integrated circuits; masks; self-assembly; 3D front-end integration; CMOS nodes; bottom-up front-end architecture; bulk flow; electrical test; film replacement etching through contact hole; mask architecture; process variability; self assembly structure; Contacts; Control systems; Electron beams; Etching; Iron; Lithography; Packaging; Process control; Silicon; Testing;
