DocumentCode :
3518146
Title :
A Novel 3D Cell Array Architecture for Terra-Bit NAND Flash Memory
Author :
Choi, Eun-Seok ; Yoo, Hyun-Seung ; Joo, Han-Soo ; Cho, Gyu-Seog ; Park, Sung-Kye ; Lee, Seok-Kiu
Author_Institution :
Memory R&D, Hynix Semicond. Inc., Icheon, South Korea
fYear :
2011
fDate :
22-25 May 2011
Firstpage :
1
Lastpage :
4
Abstract :
A novel 3D flash cell array architecture, called "hybrid 3D", is proposed to provide the distinctive low address selection method of stacked channels, suitable for conventional NAND page operation. The strings are composed of GAA type selector and double gate type cells, and their key characters were verified independently. The GAA selectors showed excellent and uniform switching character, and double gate MANOS cells were expected to provide enough program window and acceptable reliability for MLC. Extendibility of hybrid 3D was rigorously estimated within the acceptable range of channel stacking and word line scaling, where 2 Tb NAND flash memory would be available just by 16 channel stacks.
Keywords :
NAND circuits; flash memories; 3D flash cell array architecture; GAA type selector; double gate MANOS cells; low address selection method; program window; stacked channels; storage capacity 2 Tbit; terra-bit NAND flash memory; Arrays; Conferences; Flash memory; Logic gates; Microprocessors; Three dimensional displays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Workshop (IMW), 2011 3rd IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4577-0225-9
Electronic_ISBN :
978-1-4577-0224-2
Type :
conf
DOI :
10.1109/IMW.2011.5873207
Filename :
5873207
Link To Document :
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