Author :
Kar, G.S. ; Van den Bosch, G. ; Cacciato, A. ; Blomme, P. ; Arreghini, A. ; Breuil, L. ; De Keersgieter, A. ; Paraschiv, V. ; Vrancken, C. ; Douhard, B. ; Richard, O. ; Debusschere, I. ; Van Houdt, J. ; Van Aerde, S. ; Tang, Baojung
Abstract :
A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D NAND Flash memory is successfully developed. It achieves minimum cell area (4F2) without the need for pipeline connections. We introduced a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This additional silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole. The smallest working cells have been fabricated with feature size F down to 45 nm corresponding to an equivalent 11nm planar cell technology node for the case of 16 stacked cells.
Keywords :
NAND circuits; amorphous semiconductors; elemental semiconductors; flash memories; silicon; 3D NAND flash memory; Si; bilayer polysilicon channel vertical flash cell; memory hole; size 25 nm; size 45 nm; ultrahigh density 3D SONOS NAND technology; vertical cylindrical cell; Annealing; Computer architecture; Implants; Junctions; Logic gates; Materials; Microprocessors;
